Field of the Invention
The invention relates to a semiconductor structure. The semiconductor structure includes a semiconductor substrate formed of a first conduction type; first and second doped regions formed of a second conduction type disposed in the semiconductor substrate; a channel region with a surface formed in the semiconductor substrate separating the first and second doped regions; an insulation zone laterally surrounding the doped regions and the channel region; a floating gate disposed in an insulated manner on the surface of the channel region; a control gate disposed on a side of the floating gate remote from the channel region; and a dielectric layer insulating the control gate from the floating gate. The semiconductor structure of this type constitutes a non-volatile memory, a so-called EEPROM cell.
Such a memory cell is programmed (i.e. written to and erased) by the application of a potential to the externally connected control gate, which is capacitively coupled to the non-connected floating gate. A short programming time necessitates a large capacitive coupling between the floating gate and the control gate.
The realization of a large capacitance between the floating gate and the control gate is associated with a large space requirement in known cell configurations in which the control gate is configured in a planar manner on the floating gate. A sufficiently large coupling capacitance is achieved by the lateral extent of the floating gate being much greater than the extent of the active zone (that is to say of the doped regions and the intervening channel region) of the cell. The requisite area is typically about 3 times as large as a channel region, and the integration level in a memory configuration having a multiplicity of neighboring memory cells of this type is thereby limited.